I need an RF synthesizer to generate RF from 500 MHz to 4 GHz with chanel spacing of 10 KHz or less. The phase noise mask for the LO output is -90dBc @10 kHz, -110 dBc @ 100 kHz and -120 dBc @ 1MHz.
Frequency settling time after an arbitrary frequency jump has to be < 1ms worst case.
The reference clock @ 122,88 MHz (already designed and measured) can be modeled in ADIsimpll in point/floor mode using these parameters:
PN Floor -161 dBc/Hz
Phase Noise -115 dBc/Hz
at frequency 100 Hz
Flicker corner 200 Hz.
Whith these parameters the resulting phase noise matches very well the measurements.
I want to use an ADI part because of readily available drivers and support, and I found ADF4351 and ADF4355-2 as candidates.
I'm using ADIsimpll for designing the synthesizer and I've found that ADF4351 is more than fast enough when changing frequency but I can't get the simulated phase noise low enough to be compliant in the whole frequency band.
On the other hand I can get the ADF4355-2 to be phase-noise compliant with even 10 dB of margin but lock times are too long due to the autocalibration process if I want to be within the datasheet limits of the parameters related to the autocalibration.
I would prefer to use the ADF4351 because it has lower power consumption, requires one less power rail, is cheaper and I've already used it succesfully in other designs.
Is there a way to reduce ADF4351 phase noise or ADF4355-2 lock times? I've played with loop filter bandwidth and topology, PFD frequency and such and I haven't been able.