I am having trouble grasping the internal FPGA timing constraints in relation to adc_clock, adc_valid and adc_data lines comming from the AD9361 Core. I have only been working with FPGAs for a few months and from my understanding adc_valid and adc_data would need to be asserted at some time before the rising edge of the adc_clock so the FPGA can sample the data and valid lines properly.
My confusion starts with the ADC interface diagram located at: https://wiki.analog.com/resources/fpga/docs/hdl#using_and_modifying_the_hdl_cores
Everything is changing states at the same instance. Am I right in assuming
that the no-os software digital tune function will either delay the adc_clock or adc_valid and adc_data until the adc_clock rising edge is occuring after the data is setup?
Also, If I were to use your simple custom FIFO interface and use the adc_write_address as the address input to a BLOCK RAM input with the adc_clock as the BLOCK RAMs clock. It would seem like the adc_clock rising edge would happen at the same time as the address is asserted to the BLOCK ram.
If I simulate the ADC interface outputs as they are shown in the above link and use a simple FIFO similar to the verilog one you provide and integrate it into one of your HDL projects that meets timing before the addition. Will Vivado insure that the internal clk and data setup and hold requirements are met?