I need to know how to vary the sampling frequency of AD7683?
It is written that the sampling clock is internal.
I need to use this for 1KHz and 256Hz sampling,is this possible?
See my response below for your queries.
1. Although the eval board uses the Altera's Flex 6000 series, the AD7683/85 are compatible with the SPI, QSPI, digital hosts, and Blackfin® ADSP-BF53x or ADSP-219x. The SPI protocol became a standard de facto that was developed by Motorola, but It does not have an officially released specification or agreed by any international committee.
2. You don't need to worry about the settling time for this application.
3. As I recommended earlier, the AD7685 is a better fit for your application.
4. See (1). Usually, our ADC can use either 3-wire or 4-wire SPI interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections, useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. When conversion is completed, the AD7685 enters the acquisition phase and powers down. In other words, When CNV goes low, the MSB is output onto SDO and the remaining data bits are then clocked by subsequent SCK falling edges. So, the SPI clock does not need to be active during the conversion.
Hope this makes sense.
BTW, We have couple of CFTLs done on the AD7685 that may be helpful. Here are the links:
Hi Chaitanya, The AD7683 has a Serial Data Clock Input - DCLOCK. You can vary the sampling frequency by changing the speed of a clock to DCLCOK input Since the conversion result on DOUT pin is synchronized to DCLOCK. Note that the AD7683 is compatible with SPI®, QSPI™, digital hosts, MICROWIRE™, and DSPs. The connection diagram is shown in Figure 25 and the corresponding timing is given in Figure 2 of the datasheet. A falling edge on CS\ initiates a conversion and the data transfer. After the fifth DCLOCK falling edge, DOUT is enabled and forced low. The data bits are then clocked, MSB first, by subsequent DCLOCK falling edges. The data is valid on both DCLOCK edges. The AD7683 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in Figure24 in the datasheet, so this makes the AD7983 ideal for low sampling rates such as 1KHz and 256Hz (even of a few Hz). Hope this helps. Regards,Maithil
The AD7683 has a Serial Data Clock Input - DCLOCK. You can vary the sampling frequency by changing the speed of a clock to DCLCOK input Since the conversion result on DOUT pin is synchronized to DCLOCK.
Note that the AD7683 is compatible with SPI®, QSPI™, digital hosts, MICROWIRE™, and DSPs. The connection diagram is shown in Figure 25 and the corresponding timing is given in Figure 2 of the datasheet.
A falling edge on CS\ initiates a conversion and the data transfer. After the fifth DCLOCK falling edge, DOUT is enabled and forced low. The data bits are then clocked, MSB first, by subsequent DCLOCK falling edges. The data is valid on both DCLOCK edges.
The AD7683 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in Figure
24 in the datasheet, so this makes the AD7983 ideal for low sampling rates such as 1KHz and 256Hz (even of a few Hz).
Hope this helps.
What it means is that I can not sample the ADC continuously !
What I understood from you is DCLOCK is the one which decides the sampling.
Is this correct?I mean DCLOCK can go in MHz (1.2MHz) how it will work then?
Usually it is some down conversion of DCLOCK can sample this.
This is good for Single Shot mode.
I have few questions
1.It means that Micro Controller's SPI will be continuously busy by giving the clock at desired sampling rate.
2.We can not put anything else on that SPI as the clock will be too slow
3.Aperture Jitter will be there as the sampling clock is derived from DCLOCK.
4.What is the use of internal clock mentioned at the start of the Datasheet.
5.Is there any EOC ?to interrupt the DSP?
Pls keep this thread alive !
Usually the SPI clock is just for reading the Sampled data.It can be of any value and periodically DSP will read it by giving a high clock data quickly so that it can use the SPI bus for other ADCs or devices.Sampling is done by an internal or external clock with or without PLLs,results are just made ready in the SPI buffer to read.
Pls comment in the point of contiuous reading of the ADC ,probably with a seperate crystal.
This particular device uses the SPI clock (DCLOCK) as the clock for the conversion. You can run the DCLOCK up to 2.9MHz. The sample rate is determined by the /CS signal than by the DCLOCK signal, as you can run the DCLOCK at the higher speed (2.9MHz) for any sample rate you choose. Using 1kHz sample rate as an example, and a 2.9MHz DCLOCK, the transaction will take ~8.3us (24 clocks @ 2.9MHz). The rest of the time (out of the 1ms period) will be available for the SPI to be used for other devices. Given that this is a sucessive approximation ADC, the input is sampled at the falling edge of /CS and held for the entire conversion, thus jitter on the DCLOCK has little effect on the conversion. I believe the internal clock mentioned in the data sheet to be an error. I'll try to verify.
I think Tim has already addressed some your concerns.
First off, I'd recommend you to use the AD7685 for your application, which is a higher speed -250KSPS part with more functionality at the same price. It has two modes - CS mode and chain mode. It also has a BUSY signal indicator to interrupt the digital host and trigger the data reading.
Keep in mind that a minimum of 22-clock cycles are required for AD7683 16-bit conversion and DOUT goes low on the DCLOCK falling edge following the LSB reading.
Let me clarify that you can control the sample rate with CS and then serial clock has an effect of that in terms of conversion time.
As I said before DCLOCK is an input of the AD7683, so you will have to provide an external clock. I wouldn't worry about the jitter here as this is a low-speed application. The internal clock mentioned in the datasheet is not an error. Usually there are two types of clocks in our SAR ADCs -one internally generated for the conversion and one applied externally to read back the data -both of them run asynchronously. The AD7683 doesn't have the capability to generate interrupt or BUSY signal.
What's your end application?
I am bit confused.
My application is automotive diagnostic,telematics and measurement,ECU related etc.4 Bridge Sensors then MUX(4:1 x2) and instru AMP and a ADC.
I need to detect vibration,shock,sudden accleration and tri axial accleration.
I am in selection process.As you know automotive application is cost sensitive especially in India.
Presently I am using BF537.
See if I assumed TIM's explanation that the ADC conversion process is CS/ dependant.You make 1KHz timer and in its interrupt just do a SPI read of the device which will automatically make the CS/ low and SPI clock will be in MHz may be as he suggest 2.9MHz so I willl get the result in SPI data register of the processor.
This brings me back to the same question how the device knows the samplig clock ? as 2.9MHz is just a communication clock or is it that the device will sample in the intervals of 1KHz but sampling clock of 2.9MHz.So sampling bursts of 2.9 MHzs at 1KHz something like that.
As per Maithil 22 times the serial clock is the sampling clock,
2.9MHz / 22 does not make 100Ksps. I think it will be 2.2 MHz clock to get 100 Ksps and for 1Ksps 1K*22 = 22KHz so again pretty slow SPI clock needed.
This again makes me think that this particular device is may be for Single Shot mode only.Was this device targeted to particular OEM and not for a general market?
I request both of you to express your thoughts, I am bit slow on things.
So sampling bursts of 2.9 MHzs at 1KHz something. This sums it up pretty succinctly. So you'll want to set up a timer to trigger a conversion every 1ms (1kHz sample rate). The conversion is performed by performing an SPI read (at least 22 clocks, typically one would provide 24 clocks). The speed of the SPI clock (DCLOCK) can be any rate you choose, up to 2.9MHz.
I think I got it finally
Few other things I found:
1.AD7683 can not be interfaced with ADSPBF537 as we have only 16 bit SPI register and we can not store 24 bit result into this register.It is also not possible to give 24 bit clock. CS/ can be some external port pin and can be low for any amount of time.But this is not possible for SPI SCK and SPI data.As soon as the SPI is initiated it will start loading the data it can be FF as the line can be high or any data on SPI.It is always the first 16 bits will be loaded into SPI RBDR with Clock.
I don't know how the datasheet says compatible with BF53x.Even the Eval board uses some other unknown DSP kit.
Is there any other way to make it compatible with the BlackFin ? SPI is not TM which means it is not standard Motorola SPI.
2.The Settling time requirement highlighted asks to check for 0.0015% for capacitive array load.The Capacitance in pF is not mentioned.
I am using AD623 it gives settling time graphs.I am not sure it gives for 0.0015% of Vstep or not?
In my application I think I need not worry about the Settling Time as it is just 1KHz sampling .Pls confirm this !!
3.AD7685 is a fantastic option as it has 0.6 LSB INL at the same cost and a higher sampling also. It has 25MHz SPI it suits with my SD card clock.
4.AD7885 Serial output waveform Shows it is 16 bit SPI.It means it is compatible with BalckFin and SPI (TM).It does not need SPI clock to be active during conversion.Pls confirm this as I need a ADC to be compatible with BlackFin BF537 and I am planning for rigorous DMAs.
Pls give your expert opinions !
Yes this makes lot of sense.I will not use AD7683 for sure thanks for AD7685 suggestion and explanations.
My team is trying to read AD7683 and BF537 EZ kit over SPI.It looks like it is not possible to read this on BF537.
When we connected a FPGA and with which we can generate any type of serial interface,so we generated timings similar to what is mentioned in Datasheet,we got the results.
Blackfin will never be able to generate such timings over SPI.
This is the precise reason because of which you might be using Altera eval board.
Data sheet probably means Glued compatiblity with BF53x.
Has anyone performed a SPI read of AD7683 over BF53x?16 bit SPI register and 24 bit clock requirement for 16 bit data?
What we can do here is put CS/ low and read it three times in 8 bit SPI mode and keep doing this continuously as we need to supply the clock.
I don't know whether this will work?
Before I do similar exercise over AD7885,I just need to ask you a very simple question:
1.Can we interface AD7885 gluelessly to BF53x?
CNV, which initiates the conversions, to be independent of the readback timing (SDI).
CNV, which initiates the conversions, to be independent of the readback timing (SDI).
What is the meaning of that?
Do I have to do a Low high and Low of the CNV?
In SPI most of the Time the CS/ or CNV will be high so what will the device will do,keep continuing the conversion??And of what data?old acquired data again?
When we use DMA reads,I don't think we can play with CS/ and toggle it between every read.
Pls tell me suitable method to do a simple typical BlackFin SPI read of the device.
Sorry for the delayed response as I was out on a vacation.
I am not sure why you can't read AD7683 data over SPI using the BF537 EZ kit.
To answer your other questions,
1. You should be able to interface the AD7685 with the BF53x.
2. The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high and the chain mode is selected if SDI is low.
As shown in the figure below, SDI is high and it could be useful to bring CNV low to select other SPI devices, such as analog multiplexers, but CNV must be returned high before the minimum conversion time (0.5us) and held high until the maximum conversion time (2.2us) to avoid the generation of the BUSY signal indicator. When CNV goes low, the MSB is output onto SDO, which is synchronized to SCLK. The remaining data bits are then clocked by subsequent SCK falling edges.When conversion is completed, the AD7685 enters the acquisition phase and powers down.
Which mode are you planning to use? with or without busy indicator?
I'll defer you to Blackfin processor folks for an advise on suitable method to do a simple typical Blackfin SPI read of the device.
Thank you very much for being there !
I am using the AD7685 in CS mode and not in chain mode.I was using Three wire mode and hence SDI was not a concerened (held high).
I will prefer the Busy indicator as it can save my bits.Still I need do a 24 bit SPI read (3 x 8bit reads or 2 x16 bits) as more than 16 clocks are required to read the waveform.
The Busy isn't a interrupt in reality as I still have to put a timer for the CNV start and then make low high and low after words I get and interrupt from Busy,so that now I can start the SPI read and probably I will get the correct data of 17 bits where the 1st bit is always low.So I need to make integer reads of 8 bit so I read 24 bits and shift out the first bit and last 7 bits.This will eat lots of MIPS and waste lot of memory. I am not running BlackFin at high speed for Battery operation.
See I am confused the both ADCs seems to be made for SPORT interface where we can generate the 32 bit reads and Frame Syncs can generate the CNV in low,high and low, pulse type and even continuous clock is possible, however I need to use the SPI as other peripherals like SD card don't support SPORT.In SPI usually we don't play with the Chip Select it is Just low once and read the data.In BlackFin we have 16 bit register so I can read max 16 bits at a time.
I am not sure in SPI DMA we can play with Chip Select as the Datasheet says low then high and then again low.
If some of your team mate can give me a pseudo or Blackfin Code to read the ADC in SPI DMA and non DMA mode it will be very much useful.
In my board I am keeping arrangement for 3 wire as well as 4 wire mode any reference code is suitable.
For comparison I am adding both the figures we can see easily the SPI difference.
Above is Blackfin for 8 bits and can do similar 16 bits.
This is AD7685. See the Chip select(CNV and SPISS) difference.I don't find any mode of AD7685 is BF compatible for Chip select,16 bit reads and clock.
I have forwarded your query to our DSP folks. I will get back to you as soon as I hear from them.
Thanks for your patience.
finally it worked. the ADC works in DSP mode or Frame Mode.
The DMA code wasn't really useful. Anyways you cleared everything in depth.
Thanks Once again
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