I'm planning to clock AD9634 straight from an FPGA at LVDS18, does anyone see a problem in that? Datasheet mentions "If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock", but how low is "low jitter"? Is the only effect of jitter on SNR as Figure 56 (AD9634-250 SNR vs. Input Frequency and Jitter) shows? Should I check my FPGA clock jitter according to that graph?