According to the datasheet of AD9954, there is a (1mA load) specified for the CMOS logic outputs (page 6). I am assuming that 1mA is the CMOS driver's drive strength.
I want to interface these signals (i.e the SYNC CLK signal) to another device on another board (i.e FPGA) via a PCB trace and cable, I would like to employ a termination scheme such that signal integrity is preserved for the AD9954 output signals.
However, if the drive strength of the AD9954 CMOS drivers are only 1mA, I cannot use a 50 Ohm termination to ground, as the current sourced from the driver will exceed 1mA at that point.
Can someone advice on how I should interface these signals (SYNC CLK is the important one) to another device.
i.e: what kind of termination schemes should I employ?
i.e: or anything else I can do to preserve SYNC CLK signal integrity?
Thanks in advance.