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configuring ad9361 in adfmcomms

Question asked by rahulram on Nov 20, 2015
Latest reply on Jul 14, 2017 by AdrianC

hi,

    i am using fmcomms4 board along with zc706 xilinx board on no-os platform provided on the adi site. i have used the reference design given for the board and am getting a sine wave on the ila provided and have completed all the steps upto now .now i have problem extracting the data from adc as it is showing the same data recieved on both i and q two times repeated when the data is extracted. my problem is that i have to send custom data from tx on ad9361 and recieve that data on rx without using the dac_dma and adc_dma blocks in the design . to some point i have been able to do  this . but when i try to send my data i am not getting the expected data at the adc output on ad9361 block . i think this might be the problem with the clock at which the ad9361 might be transmitting ,can anyone tell me what is the output of l_clk signal coming out of ad9361 block in design which is given back to the clk input,how can i change the value of l_clk. i want to send data from my custom block at the rate of 20 mhz but when i change the clk input of ad9361 block i get an error in console saying tx an rx tunning failed and ad9361 failed to intialize .can anyone tell me how to solve this problem .thanks

 

 

regards

rahul

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