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AD9106 RAM address incrementing

Question asked by yorkpa on Nov 18, 2015
Latest reply on Nov 19, 2015 by larrywelchusa

A couple questions about incrementing the address of the RAM. Ultimately, I want to increment the RAM at a rate slower than CLKP/CLKN.


1) Normally the DAC clock increments the SRAM, but the datasheet suggests that the MSB of the DDS can also be used (DDS_MSB_ENy in DDSx_CONFIG). This would be cool, because lower frequency signals could potentially be generated. But, setting (DDS_MSB_ENy) doesn't seem to change the clocking. Is DDS clocking of RAM only allowed when WAVx_yCONFIG is set to output "prestored waveform modulated by waveform from RAM"? This could be implied by the section "Incrementing Pattern Generation Mode SRAM Address Counters" on pg. 27 of Rev. A of the data sheet.


2) What do the HOLD bits of PAT_TIMEBASE do? I thought they would allow the RAM output to be held for multiple clock ticks, but that does not seem to be the case.


3) Is there any other way to change the address increment rate?


Ultimately, I might just run into the limit of the pattern generator: "The longest pattern period available is 65535 × 16/(FCLKP/CLKN)." (pg. 25, Rev. A). So to generate low frequency signals, the most straightforward thing to do might be to do some external clock division.


Thanks in advance for your help! It's a great chip, just a little annoying to figure everything out.