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ADP5052 power sequencing constraints for chanel 1

Question asked by dmarcosgon on Nov 18, 2015
Latest reply on Nov 19, 2015 by hyao



I have to design the supply of a system where the ADP5052 fits very well, but I have a doubt about power sequencing.  In my application, PVIN1=PVIN2=PVIN3=PVIN4,  all these power input pins are tied together to the same input rail. I need to generate 4 output voltages, V1, assigned to chanel 1, V2, assigned to chanel 2, V3 assigned to chanel 3 and V4 assigned to chanel 4. The voltage-to-chanel assignation has been done to maximize efficiency due to different current needs for each voltage rail.


The power sequencing scheme requires that V3 (chanel 3) starts first, and when it reaches a certain threshold the rest of the chanels need to be enabled (the sequence would be V3 and then V1, V2 and V4). Reading the datasheet of the ADP5052 it looks like as long as PVIN1 is present (which it is) you can sequence the chanels as you please by using the precision enables for each chanel, but I'm not 100% sure if im right here or if chanel 1 must always start first. I could map V3 to chanel 1 but that would mean sacrificing efficiency and performance, and current requirements for V1, which would have to be maped to chanel 3 in this case, are close to the 1.2A limit for this chanel.


Could you please confirm that my required power sequencing can be done on ADP5052? Thanks.