I am using the ADI_FMCJESDADC1-EBZ reference design with a ZC706 evaluation board. I am trying to figure out why the frequency of the adc_clk signal is not 245.76MHz. According to the users guide, one of the outputs of the AD9517 is set to the ADC's sample rate (245.76MHz) and sent to the ZYNQ chip via the FMC connector. This is an LVDS signal pair that passes through a differential input buffer and enters the block design as a signal named "rx_ref_clk." From here, it enters the axi_jesd_gt module (I am using version 1.0), and it exits on a pin called "rx_clk_g." This signal is sent outside the block design as a signal named "adc_clk."
I have sent both signals ("rx_ref_clk" and "adc_clk") to an SMA port on the ZC706 so I see the signals on an oscilloscope. It looks like "rx_ref_clk" is running at the specified frequency of 245.76MHz as expected. However, "adc_clk" seems to have a frequency of about 122MHz. I thought that "adc_clk" was the recovered clock signal that was sent from the AD9517, so I was expecting it to be at 245.76MHz.
Is "adc_clk" the clock signal I should be using to clock the ADC samples into my HDL?
If so, why is it at half the frequency of the ADC sampling frequency, and where does this division happen?
If data is coming into the ADC at 245.76MHz, but the samples are being clocked into the PL of the ZYNQ chip at half that frequency, why doesn't it miss every other sample?