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Timing Violation - FIFO to dac_data input

Question asked by vittal92 on Nov 17, 2015
Latest reply on Dec 2, 2015 by rejeesh

Hello,

 

I am integrating a custom core to the FMCOMMS3 in order to Transmit and receive custom data.
I am being able to interface the core to the ad9361 module in the reference design. However, I have some issues regarding the same.

 

    The Data path is as follows: Custom core --> FIFO --> dac_ data
    The custom module has an output frequency of 1.302 MHz which I use as my sampling frequency.
   (The input clock to the custom module is provided by dividing the ad9361 clock (125Mhz). There exists a clock divider inside the custom     module which outputs the I and Q data at 125/96 = 1.302Mhz)
    The write clock for the FIFO is set at 1.302 Mhz and the read clock is equal to the ad_9361 frequency (which i believe is 250MHz) 
    After implementation, I see some timing violations in the following path: FIFO- Data_out  to dac_data_in - Setup violation

Has this kind of issue been seen earlier? Could you please suggest some ways to fix the same.
Please let me know if I need to provide any other information.
Thanks

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