I'm trying to use necessary cores (ad9361,adc dma,ddr,..) at new opened vivado project. I connect the cores same way at the hdl reference design.(hdl ref 2014.2) I have KC705
Why i get this timing error?
"There are timing errors in reference project." -- This is false, none of our released project have any timing errors. Can you share some timing results with us, to confirm your statement?
If you modifying things, you need to know what you are doing. I you are not too confident with the tool (in this case Vivado), try to do incremental modifications. Just one small modification at a time. Start with an unmodified project, and delete all unnecessary core from it, one by one, making sure, that after you delete one core you actually delete all related signals too. After every step make sure that you can generate a bit stream without a problem.
You need to be able to generate a tcl file from your block design, if you not, that means you have other bigger issues, what you need to solve first.
If you have a timing related problem always share a timing report with us, other wise we can not make any conclusion at all about your problem.
I would recommend to take a step back, and start everything over, from scratch.
You should try to generate a log file or timing report and share that with us.
I modified reference design (for example i added fft core or just deleted unused hdmi,spdif cores) and i get timing error.
Also i designed a new project from start using necessary cores, i get timing error too.
How can i attach timing reports because too long, is there any dedicated e-mail address to share with you?
Thanks a lot.
The docs are in the attachments.
It looks like, you're missing some constraints files.
Please run the following command in the TCL console, while you're implemented design is open and share the result with us:
join [get_files -compile_order constraints -used_in implementation] \n
I have 2 xdc file which are manually added.
Also, i didn't check any cores' generate board constraints, i added manually.(i.e. uart,spi)
all files attached.
You have a lot of failed path inside of both DMAs. How you set up the DMAs? Instead of sharing a print screen of the block design, can you generate a tcl script from it, and share that, please?
write_project_tcl normally work.But there is a problem about this project. I shared 7zip file instead of tcl of the project.
Thks a lot
create_clock -name ad9361_clk -period 4[get_pins_axi_ad9361/clk] missing my constraint file.
Is it possible the error is related to this missing line?
That constraint have to be included in your constraint file. Please add it and give it another try.
I added it,unfortunately didn't work.
There are errors that;
mmcm_clkout0 to rx_clk
rx_clk to mmcm_clkout0 under inter-clock pats.
mmcm_clkout0 to rx_clk under other path groups/async_default
We set rx_clk period4 in the xdc file.(Why?)
The error may be related to this settings?
Also i want to say,
There are timing errors in reference project. But design runs tab doesn't show any timing errors??
Can Edit timing constraints help us?
(Why we create rx_clk and ad9361_clk clocks?)
Thanks for advices,
You are absolutely right. There is no timing error in reference hdl's.
1) from zero with necessery cores
2) via deleting unncessary cores from design
Both of them generated without any timing issues:)
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