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Timing failed HDL reference

Question asked by berker on Nov 17, 2015
Latest reply on Nov 20, 2015 by berker

Hi,

I'm trying to use necessary cores (ad9361,adc dma,ddr,..) at new opened vivado project. I connect the cores same way at the hdl reference design.(hdl ref 2014.2) I have KC705

 

Why i get this timing error?

timing.jpg

Thanks

Berker

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