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Question asked by Makawi on Jun 10, 2011
Latest reply on Apr 4, 2013 by julietaflom

Hi !


I’m just trying to find what the better REFCLK input would be for getting the lowest jitter output, and several questions rose. Different possible configurations with respective doubts are next:


1) Use a quartz

Are external capacitors necessary? (Par example, AD9951 recommendations are to use two 39pF capacitors to ground).


2) Use an external oscillator


First of all:

From Datasheet: “REFCLK Input Voltage Swing Full IV 100 1000 mV p-p”


What’s the exactly meaning of “REFCLK Input Voltage Swing”? I don’t understand how DDS can not admit values greater than 1 Vp-p, when usual outputs oscillators are really beyond this value. Perhaps I’ve misunderstood that.


2A) Use an usual commercial oscillator (of about 50 ppm frequency stability).


These oscillators have an output of about Vdd (usually Vol = 20% Vdd  and Voh = 80% Vdd). As normally Vdd is 1.8V, 3.3V or 5V, these values are much over 1000mVp-p REFCLK input limitation. So it’s not possible to use this kind of oscillators.


2B) Use a clipped sinewave output temperature compensated oscillator (of about 1-2 ppm frequency stability).


All of these have a 0.8 Vp-p output. It seems nice but I think (I don’t know much about this issue) it can’t be directly connected to DDS because it has a slow slew rate. I’ve read that it’s “mandatory” to amplify it to improve the slew rate. But if we do that, we’re going to be still out of range (much over the 1Vp-p REFCLK input limitation)!!! So it’s not possible either to use this kind of oscillators!!!


Finally, and supposing all above configurations are possible, which would be the one with a better jitter performance output?


Thank you very much,