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Sample Timing Slip

Question asked by jsaylor on Nov 16, 2015
Latest reply on Nov 24, 2015 by tlili



I have found an issue with the AD9361. It appears to have a issue starting up with a consistent amount of delay. Below is a plot that was generated by sending a waveform in loopback fashion. Both RX and TX were configured to start at exactly the same time. (I have developed the HDL modules/ SW drivers to do this) I have verified also with the ILA tool (formerly Chipscope) that data through the TX path reaches the dac interface exactly when expected consistently. The inconsistency is observed at the adc interface. Somewhere in the AD9361 HDL or AD9361 chip data is not consistently flowing through a pipeline (IMO it's the chip based on multiple projects have a similar experience).


Kind Regards,