I'm having a bit of an issue getting consistent timing through the AD9361 HDL module and chip. The time I am measuring is from the dac interface to adc interface in a loopback is inconsistent. (see attached figure)
I've created a HDL module to track time and timing modules to start TX and RX operations at specific times. I have created a test to measure the path delay base on the time it takes for an input waveform to travel through the system. To do this I begin a TX and RX at the same time and measure the time in which it takes for the waveform transmitted in the TX to be found in the RX. I measure the time in samples clocks (38.4 MHz/~26ns). Using the Vivado ILA I have observed data getting to the AD9361 dac interface but the time it takes to return to the adc is nondeterministic. Below is a figure generate when I do 9 loopback tests. Sometimes the data arrives 58.2 samples after it is initially transmitted and other times it takes an extra sample clock (~26ns) to complete the loopback.
I also have save the ILA captures to present if someone would be interested in looking at them... It demonstrates that the data appears consistently at the DAC interface at the same number of clocks from the start time, but inconsistently appears on the ADC interface.
Other things to note:
My center frequency doesn't effect this characteristic, however if I alter my center frequency in between each loopback this issue occurs less frequently.
If there is more documentation on the AD9361 HDL Design (more than just the register map) I would like to give it a read through.