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ddr3 constraints and using 9361 at seperate design

Question asked by berker on Nov 16, 2015
Latest reply on Nov 17, 2015 by CsomI

Hi , I've 3 questions

 

I use hdl2014_r2 fmcomms2.

 

1) Why 5 pins od DDR are connected constant values?

ddr3_p0 <- 1

ddr3_p1 <- 1

ddr3_n0 <- 0

ddr3_n1 <- 0

ddr3_n2 <- 0

 

** Should  do i same way at my custom design also?

2) I want to port 9361 core to a another design. Which cores need also to carry my new design to see I&Q datas ? I think these are should;

 

spi core

uart

gpio_fmcomms2

ddr cont(mig)

 

3) What is the functionality of axi iic core ?

 

Best regards

Berker

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