Hi , I've 3 questions
I use hdl2014_r2 fmcomms2.
1) Why 5 pins od DDR are connected constant values?
ddr3_p0 <- 1
ddr3_p1 <- 1
ddr3_n0 <- 0
ddr3_n1 <- 0
ddr3_n2 <- 0
** Should do i same way at my custom design also?
2) I want to port 9361 core to a another design. Which cores need also to carry my new design to see I&Q datas ? I think these are should;
3) What is the functionality of axi iic core ?