Our customer is putting your AD9826 on their product video camera.
He is using for AD9826 by 2 channel CDS mode.
So here is question.
What does the problem coming to drive by following ADCCLK you think?
L=40ns (not 60ns !)
(1cycle=180ns as 2 frequency)
Fig-3 on youe datasheet seems to shows duty=50% of ADCLK.
If ADCLK decide the clock by output timing of D<7:0>, so is this no problem?
I need your comment.