I am using ZC706 and FMCOMMS2. Iam using hdl-hdl_2014_r2. I want to add my signal processing IP core between util_adc_pack core and axi_ad9361 core. I went through this link ADI Reference Designs HDL User Guide [Analog Devices Wiki] and found the interface details. I am planning to use adc_clk , adc_enable , adc_valid , adc_data . I am planning to use these signals like a FIFO interface - adc_clk as fifo write clock ; adc_valid as fifo write enable. adc_enable will be directly routed to util_adc_pack core .
Iam confused about what to do with adc_ovf (Data overflow) signal. Should i keep it as in hdl-hdl_2014_r2 (direct connection from axi_ad9361 core to axi_ad9361_adc_dma core). what is the main purpose adc_ovf used.
I added an ILA to study the interface and given signal using IIO scope, then adc_ovf signal was coming frequently. Is this signal important.
Please give me your advice