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AD9361 LPC interface clock rate

Question asked by jsn on Nov 9, 2015
Latest reply on Nov 11, 2015 by larsc

Hi,

 

According to the AD9361 datasheet, each 6 pairs DDR LVDS interface can clock up to 245.76 MHz. Using 2 * 6 pairs allows to make 2x2 MIMO FDD with up to 61.44 MSPS.

 

On the FMCOMMS2, it seems these 2 * 6 pairs LDVS interfaces of the LPC interface are clocked at only 122.88 MHz.

Please see the block diagram on the wiki.

https://wiki.analog.com/_detail/resources/eval/user-guides/ad-fmcomms2-ebz/cf_ad9361_zc706_bd.jpg?id=resources%3Aeval%3Auser-guides%3Aad-fmcomms2-ebz%3Ahardware%3Afunctional_overview

 

This limits 2x2 MIMO FDD to 30.72 MSPS.

 

Why these LPC interface pairs are clocked at only 122.88 MHz ?

Can we increase this clock rate up to 245.76 MHz ?

If not, why ?

If yes, can this rate work with the Zynq 7010 as we have on the Zedboard ?

 

Thanks a lot for your kind help and support.

 

Best regards.

 

Jean-Samuel.

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