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AD9361 DAC operation in axi_ad9361 module

Question asked by smoki on Nov 9, 2015
Latest reply on Nov 9, 2015 by DragosB

Hi all,


I'm working with AD9361 integrated with Xilinx ZedBoard. I made HDL design using this project(analogdevicesinc/hdl · GitHub) projects->fmcomms2->zed. Also run SDK with this software(no-OS/ad9361 at master · analogdevicesinc/no-OS · GitHub).

I'm trying to send LUT values on TX1 port, to see sine wave on oscilloscope. I have one thing that I can't figure out how it works. I'm wondering how axi_ad9361 module "converts" dac_data_i0[15:0] & dac_data_q0[15:0] to six bit tx_data_out_p & tx_data_out_n signals? tx_data signals goes to ad9361 to generate analog signals, right? Can you direct me where can I look this in detail, please?

Also, I see that sine wave carrier frequency is 2.5GHz(default value), but what are the sine frequency and sampling frequency values? And where to read/modify these values?


Best regards,