I intend on using the AD9484 in a multichannel digitizer/processing system.
8-bits running at 500Msps is great for this purpose.
I was looking through the datasheet of the chip and the eval board and still had some questions. Even after looking at other threads on this chip.
1. clocking and data lines.
I am pin constrained, so I wanted to leave out the OR line and the DCO line. I have multiple chips so I planned on routing a single copy of the sample clock to the FPGA and fix the timings of all of the data lines in the FPGA afterwards.
This is, in my opinion, possible if the 'Tpd' time stays fairly constant.
Does this make sense?
Also, if I don't use the DCO line, do I still need to terminate it, or should I just leave to open?
2. DC coupling a diff amp.
For this application I need to go down to DC, so I can't use a transformer or anything. In the datasheet an example using a diff amp is mentioned at figure 28.
Now the Vcm is mentioned in the text and it says AVDD/2 + 0,5V that is 1,4V which is fine by me. But in figure 17, 1,4V is not even on the graph! I find this a bit weird. It's clear that the SFDR has an optimum around 1,7V, but as long as I have an SFDR of 60dB it's no issue.
Can any of you say anything about this?
Figure 21 suggests that the 1,7V is always present on the CML pin. And a user could couple that to the midpoint of the two 500ohm resistors by setting a register bit via the SPI port.
Table 12, address 0x2C contains this bit, it's set to 0 by default. The text says 'Default is AC coupling.'.
Does this mean that the connection to the midpoint of those resistors is there by default, or is it the other way around?
The reason why I ask this is because I would like to run without an SPI port if possible. That would save some pins.
Thank you for your time!