I'am using Fmcomms2 reference design for ZC702, now I have to know the width and deepth of the FIFO in adc and dac dmac block.
Please help me.
Just to add, the FIFO in the DMAC is not used for storing data, it is used for as a store and forward buffer to the main memory bus and also for compensating jitter and latency on the main memory bus. It is sized so that the design at maximum data rate is able to sustain continuous memory transfers without loosing any data. The FIFO size does not affect maximum transfer length or similar. Thus form the applications point of view the size itself is pretty irrelevant.
input/output width: 64
depth: 4 bursts
max bytes per burst: 128
Thanks for your addition.
I can only a small part of DDR with a lot of data, so I need to refresh the received data in DDR . But FIFO will be full during refreshing DDR , that leads to lose continuous data . So i want to know the deepth of FIFO and try how to get continuous data with a small part of DDR. Do you have a good idea?
What kind of DDR are you using?
If the refreshing increases the write request jitter, but your overall average write request throughput is still high enough to sustain continuous streaming, increasing the number of bursts that the FIFO can hold will solve the issue.
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