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Have you any JESD204B reference design that has not microblaze and MIG7 Axi_ddr_cntrl?

Question asked by -2dbc on Nov 8, 2015
Latest reply on Nov 10, 2015 by rejeesh

Hi all,


As I mentioned my previous post.

I have a ad6676 & kc705 setup. I need a faster ethernet speed than you provide in your reference designs.


I have two different project now and I want to merge them.

1. Xilinx' AXI_ethernet example design

2. ADI' JESD204B ref. desgin.


1. I used Xilinx' AXI_ethernet example design and I can get raw I/Q samples(ramp data for testing purposes) from KC705.

My ethernet speed is increased to 90MB/s from 3MB/s. It uses 200MHz clock.

I can get ramp data from fpga and this design works without ad6676(adc).


2. I made some changings on your jesd204b design. In summary:

rejeesh advised to me in my previous post. I implemented it.

"I don't think changing from 100M to 1G will help you here. I would think the data makes its way to the MAC the same way in both cases (via the DMA -> DDR -> DMA) -- that may be the bottle neck. A cool thing would be removing these and adding a MII interface to the ADC core - that might give you the short cut and the speed."

Now, I want to merge these two project and I have a trouble. these two project use 200Mhz clk_in_p and clk_in_n independently both of them. And merged design throws an error like this:

[Place 30-602] IO port 'clk_in_p' is driving multiple buffers. This will lead to unplaceable/unroutable situation.

The buffers connected are:

UDP_block/example_clocks/clkin1_buf {IBUFDS}

system_top_ins/i_system_wrapper/system_i/axi_ddr_cntrl/u_system_axi_ddr_cntrl_0_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk {IBUFDS}


Your design has a block design and Xilinx' has not. Your design uses MIG7 axi_ddr_cntrl as clock source that is generated from differential clk_in_p and clk_in_n.

Xilinx' design uses 200MHz clock that is generated from differential clk_in_p and clk_in_n.

To solve problem, I think about to remove MIG7 and use Xilinx' 200MHz clock instead of this.

But all of other IP cores(AXI cpu interconnect, microblaze, sys_rst_gen ...) use MIG7's out port ui_addn_clk_0. Other out ports mmcm_locked and ui_clk are used by some IP cores also.

Jesd cores need s_axi_.... inputs and AXI_cpu_interconnect core supply these inputs.

In conclusion, I think If I remove axi_ddr_cntrl, My problem will be bigger than now and I don't want to remove it.

Have you any JESD204B reference design that has not microblaze and MIG7 axi_ddr_cntrl? 

Thanks in advance.