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AD9361 DAC Explanation

Question asked by smoki on Nov 6, 2015
Latest reply on Oct 13, 2017 by mohsinshafiq87

Hi all,

 

I'm working with AD9361 integrated in Xilinx ZedBoard, and I'm pretty much new in this area. I made HDL design using this project(analogdevicesinc/hdl · GitHub) projects->fmcomms2->zed. Also run SDK with this software(no-OS/ad9361 at master · analogdevicesinc/no-OS · GitHub).

 

The problem I have is that i can't realize how to send some data throw DAC to output of ad9361? I defined DAC_DMA and when I call function dac_init(ad9361_phy, DATA_SEL_DMA, 1); I can see LUT values in address space, but I don't know how to start conversion to send those LUT values on TX line and see it on osciliscope? Also, can someone explain me why sw make theese changes on LUT values:

data_i1 = (sine_lut[index_i1] << 20);

data_q1 = (sine_lut[index_q1] << 4);

Xil_Out32(DAC_DDR_BASEADDR + index * 4, data_i1 | data_q1);  // I have plotted this data in MATLAB and see that this is sine wave.

Where does this 20 and 4 vaues come from?

 

 

Hope that someone can help me

 

Best regards,

Nemanja

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