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AD9652 clocking at 245,76 MHz

Question asked by dmarcosgon on Nov 5, 2015
Latest reply on Nov 6, 2015 by Anthony.DeSimone



We're going to use an AD9652 in an application and we wanted to directly clock it at 245,76 MHz from the output of an ultra-low jitter clock generation and distribution system. The clock signal will be sent via LVPECL, the expected jitter is <100fs RMS and 50% duty cycle is guaranteed. Will there be any performance degradation with this configuration? I'm asking this because in the datasheet all tables and specs are given for an input clock frequency of 1340 MHz which is then divided inside the ADC to 310 MHz, and we want to directly send 245,76 MHz and not use the internal dividers.