Dear PLL specialists,
I am using the Hittite PLL chip HMC703.
The simulation results and real life measurements of phase noise vary by some dB. Taking a look into my simulation the RF Divider Noise and Reference Path Noise are ideal at -300 dBc/Hz. Modifying the RF Divider Noise brings me much closer to reality.
What are the typical values for the Hittite Microwave PLL Design & Analysis Tool for the HMC703?
Thanks and best regards,