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Running Pooled Delay Module on SDRAM (state C) Memory

Question asked by rsmith@iedaudio on Nov 4, 2015
Latest reply on Dec 7, 2015 by JJoseph

Hello,

 

I have been running various tests on the ADSP-21489 EZ-Board - and have started to test the delay block.

 

My ultimate goal is to have a delay block of up to 1 sec x 16 channels (using external SDRAM), but my first step is to get the 125ms delay running in SDRAM.

 

I started with the existing pooled delay block source code provided by ADI  and followed the instructions in the Algorithm Designer manual to build the DLM and port it into the SS app.  That worked and I was able to use the block in the SSn schematic.

 

I next attempted to map the state memory for the delay from internal to external SDRAM.  I changed pointers used from pState to pStateC in the adi_pooldelay.c file.  I modified the Memory Requirement for the Module by setting State to 0 and setting State C to 23054+7*RepCount.

 

When I built  and tested the new "state C" version of the plugin ... it does not run in the SSn.

(I modified the LDR file to use one LED as a HB light - and the app never fires up or it is locked up). 

 

I followed the other discussion related to this topic.  I noticed that there was a new AMF-PooledDelay.asm file that supposedly eliminates some illegal assembly instructions.  Tried that - did not work.

 

I also wasn't sure if I needed the ResetExtPre() / RestoreExtPre() calls at the beginning and end of the block... but that did not make a difference.

 

I am using the default memory sizes provided in the app.c and app.ldf  - from what I can tell from the blocks reserved should be enough for the 125ms delay.

 

Any ideas of what could be the problem?

 

Also some other questions related to this:

  1. Do the values entered in the Algo Designer Memory Requirement Window affect how much memory is reserved for the module at run-time?
  2. How do you derive the numbers for the memory requirement?  I see 23054 + 7* RepCount.  If I increase the size of the pool - I'm assuming this number must also increase.

 

I am using the following Hardware / Software

ADSP-21489 EZ Board

CCES 2.0.0.0

SigmaStudio 3.11 Build 2

 

Reference ADI Code:

adi_pooldelay.c

AMF_PooledDelay.asm

 

Other Topics I Reviewed:

https://ez.analog.com/message/68237#68237 ( this looks close to what I want)

https://ez.analog.com/message/157618#157618

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