I am seeing strange results when I feed both inputs of the AD9680 with the same signal.
First, my setup is as follows:
1. Baseboard: Xilinx KCU105.
2. FMC card: AD-FMCADC4
3. Sampling frequency: 1 GHz
4. Input signal: 20 MHz sine wave (split into 4 copies with resistive splitters).
5. I want to bypass DDCs, and get the "raw" signal.
6. Data captured using ChipScope and post-processed in Matlab.
For the sake of clarity, let's call the 2 cores in the first ADC chip A and B, and the 2 cores in the second ADC chip C and D.
Now, for the strange results:
1. I can see all 4 sine waves, with the correct frequency.
2. The sine waves from A and B are _exactly_ 180 degrees out of phase.
3. The sine waves from C and D are _exactly_ 180 degrees out of phase.
4. The phase relationship between the sine wave from A and C is approximately 90 degrees, but it does not seem to be locked between FPGA reprogramming.
Does anyone have any idea what is going on? My current assumption is that some register setting is wrong, but I cannot figure out which one.