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Register settings for ADV7341BSTZ for HD Mode

Question asked by NanjundaM on Nov 4, 2015
Latest reply on Nov 16, 2015 by PaulS



We are doing the register configuration for ADV7341 IC as per Table 125 in the datasheet to get a 1280x1024 resolution RGB in, RGB out in HD mode

(Register No. , Value)

0x17 0x02 Software reset.

0x00 0x1C All DACs enabled.

0x01 0x10 HD-SDR input mode.

0x02 0x10 RGB output enabled. RGB output sync enabled.

0x30 0x28 720p at 60 Hz/59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.3 output levels.

0x31 0x01 Pixel data valid. 4× oversampling.

0x33 0x2C 4:4:4 input data. 10-bit input enabled (10 × 3 = 30-bit).

0x35 0x02 RGB input enabled.


We are driving the 24 bit RGB data, P-Hsync, P-vsync from FPGA and P-blank is tied to 1 at FPGA.

We are not seeing any output. We have also configured the IC to generate an internal test pattern by writing to

0x31 0x5 but no output in either case.

Are there any other registers to be configured to get it working ?

Please help us with your suggestions.



Thanks & Regards,

Nanjunda M