Please see our scheme and give us a clue, thank you!
Here is our design:
1. We don't use REFA and REFB.
2. The VCXO always outputs 10MHz, and don't need OSC_CTRL.
3. The PLL1_OUT is OK(= 10M/2 = 5MHz).
4. PLL2 is locked
The value of Readback Register (Address: 0x22C) is "1110010".
It means: (7) PLL2 reference CLK is OK
(6) PLL2 feedback CLK is OK
(5) VCXO status is OK
(4) REF_TEST is off/clocks are missing
(3) REFB is off/clocks are missing
(2) REFA is off/clocks are missing
(1) PLL2 is Locked
(0) PLL1 is unlocked
The value of Readback Register (Address: 0x22D) is "00001000".
It means "holdover" is active.
The output of CH2 is 100KHz.
It seems the input of CH2 divider is 10MHz(10M/100=100K), not 1GHz(1G/100=10M).
But the value of PLL1 output Control Register (Address: 0x1BB) is set to "0x00", choose the VCO as CH2 divider input.
Please give us a hint or direction to debug.
Thank you in advance!