I have what is probably a simple question, yet I cannot seem to find the answer in the documentation.
I am doing preliminary design using ADV212. The '32-Bit Host Application' from the datasheet (see attached) is basically the configuration I am using. Looking at Figure 13 of the same datasheet (attached) It would appear that to do a DMA transfer from the ADV212 to the FPGA requires the use of nWE or nRD to clock the data yet I do not see how the CPU will know to begin clocking data. The ADV212 will initiate a nDREQ then the FPGA clears nDACK but how does the CPU know to begin clocking the data with nWE? Why is the CPU involved with the DMA transfer anyway? Isn't that the point of DMA?
I must be missing something simple.