In the datasheet of AD9524 , page 18, it mentions that "VCXO is from 15MHz to 250MHz".
SO, a 10MHz VCXO can not be used with AD9524?
Thank you in advance!
I'll change that phrase " to 250MHz". The max limit is based upon the PFD rate of PLL2. I hesitate to put a low limit because the low limit is really based upon the desired loop bandwidth, VCXO characteristics, etc. But 10MHz will work fine.
If we use single-end VCXO, which output is connected to OSC_IN.
My question: We should connect OSC_IN_n pin to GND through a capacitor?
The OSC_IN/OSC_INb can operate in differential mode or as a single-ended CMOS input using either the OSC_IN or OSC_INb as the the input (I doesn't matter which input). Each CMOS input can be powered down via a register bit, this powering down should provide the isolation required for any unwanted signal coupling onto the AD9524. For this reason the unused input can be left floating and powered down using the register bit.
Thank you for the rapid respond, so great!
One more question, please.
In the datasheet page 5
It mentioned that if use ac coupling, single-ended input should dc bias to 1V.
Our VCXO is a 3.3V CMOS single-ended output.
So we just directly connect VCXO output to OSC_IN, not through a 0.1uF capacitor?
A true CMOS output should be DC coupled directly into the desired input.
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