AnsweredAssumed Answered

SPORT configuration for I2S receive

Question asked by Felipe.Sarmiento on May 30, 2011
Latest reply on May 31, 2011 by Felipe.Sarmiento

Hello community,


I'm Developing an application that involves receiving an I2S stream (first left/ then rigth), 24bits each channel,

at 48Khz, on the EZ KIT 21262, in order to setup the connection, The Processor has to output the serial clock

and the word select signals trough any of the DAI pins, I selected:


DAI P1   <--- I2S Data

DAI P2   --->  Serial clock

DAI P4   --->  Word Select


Since I need to build the Serial Clock and Word select signals, I'm thinking on using the PCG to generate them,

so with external oscillator provided on the EZ 21262


(12.288Mhz) ---> DAI P5


Ok so the I2S TX is 64 cycles long, I want to sample at 48Khz, using this information I think that the PCG,

configuration should be:


Fs=48e3;                      % Sampling Frequency;    

Fsck=64*Fs;                 % Serial Clock Frequency= 3.072Mhz
Fext=12.288e6;             % External Oscillator provided with The EZ KIT 12.288MHZ
Div_ClkA=Fext/Fsck      % CLK_DIVISOR = 4
Div_FSA=Fext/Fs          % FSA_DIVISOR = 256
After this, I writted this little code for the PCG:
//NAME:     initPCG.c
//DATE:     30/05/2011
//USAGE:    This file initializes the PCG for using it as sample clock
// and frame sync.
//LAST UPDATE: 30-05-2011 First Draft

#include "tt.h"
#include <sru.h>
#include <def21262.h>
#define CL_PCGA_0   0xC0000100
#define CL_PCGA_1   0xCFC00004
#define CL_PCG_PW  0x00000080

void InitPCG(){
//Generating Code for connecting : DAI_PIN5 to PCG_EXTA

* (volatile int *) PCG_CTLA0 = CL_PCGA_0;  //FS Divisor = 256 & FS Phase 10-19 =0,
                                           //Enable Clock, Enable Sync
* (volatile int *) PCG_CTLA1 = CL_PCGA_1; //CLK Divisor= 4
                                          //   & FS Phase 0-9 =252, Use EXTA_I as source
* (volatile int *) PCG_PW    = CL_PCG_PW;  //FSA Pulse width = 128  
//Generating Code for connecting : PCG_CLKA to SPORT0_CLK

//Generating Code for connecting : PCG_CLKA to DAI_PIN2

//Generating Code for connecting : PCG_FSA to SPORT0_FS

//Generating Code for connecting : PCG_FSA to DAI_PIN4

The problem arises when I try to configure the SPORT0 to receive I2S, I was reading,
the Hardware reference manual however I dont understand how to configure the sport

      • Is  SPCTL0 the only register involved in this reception?
      • Where is the received data stored??\



I'm sorry if the question is too general, this is my first real DSP proyect and I get confused easly.