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AD9833 expected clock output jitter

Question asked by coburn on May 29, 2011
Latest reply on Jun 2, 2011 by LiamR

Hello everyone,

 

I have an AD9833 evaluation board, and have connected a:

 

  • 5th order elliptical filter (provides minimum -65dB Attenuation)
  • Comparator after filter (120ns propagation delay)

 

The aim is to produce a 2MHz clock

 

I am just wondering what sort of jitter values other people are experiencing with the device?

Currently I have a 2ns jitter, which is ok but wondering if anyone else has managed to reduce the jitter?

 

Is there any particular frequencies where jitter may get worse, for example does the amount jitter increase where the phase truncation is at a maximum?

 

Thank you

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