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BF561 start up

Question asked by Laz on May 27, 2011
Latest reply on Jun 6, 2011 by chadw

I'm confused (again).

 

In the dual-core projects in Examples, the main for both core A and B start out with setting the PLL, after core B is started.  But the guidance in EE-314 says to set up the PLL and SDRAM before enabling core B.  Before makes better sense to me.  There is only one PLL and one SDRAM interface, and Core A should set them prior to allowing core B to run.  Am I missing something?

 

From Examples\BF516 EZ-KIT Lite\Timer (C):

 

Core A

void main() {
int i;

period_count = 0;
index = 0; // this is the shared value

// unblock Core B if dual core operation is desired
#ifndef RUN_ON_SINGLE_CORE
*pSICA_SYSCR &= 0xFFDF; // clear bit 5 to unlock 
#endif

 

// set Clocks
Set_PLL( (short)(CORECLK/CLKIN), (short)(CORECLK/SYSCLK));   // sets Core clock to 600MHz (= 18 x 33MHz) and SCLK to 120MHz (=600Mhz / 5)

 

// initialise SDRAM
InitSDRAM();

 

Core B

void main() {

// set Clocks
Set_PLL( (short)(CORECLK/CLKIN), (short)(CORECLK/SYSCLK));   // sets Core clock to 600MHz (= 18 x 33MHz) and SCLK to 120MHz (=600Mhz / 5) on BUB

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