I am designing a laser ranger where the latency of the ADC matters. The ADC is clocked at 250MHz. According to the datasheet, the latency should be 8 clock cycles. Here is the problem: after every the latency changes randomly. Sometimes it is 8 cycles, sometimes 9. This remains constant until the next power cycle. The reason why I am sure the reason is not a stupid bug in my FPGA is that the FPGA is clocked by the DCO output of the ADC. Always two bytes are processed in parallel. Any shift in the FPGA can only shift the data by 8ns. Anyone encountered this problem before?