I'm working with the reference hdl design for fmcomms4. In the vivado block design there is already an ila debug core for ADC. But when I try to debug the same design using hardware manager, the debug probes are not visible and I'm getting an error saying that "The debug core is not connected to a free running clock"
NB: I didn't alter the reference design at any level.
I'm using no-OS set up and I tried to associate the elf file to generate a new bit file, which I used for debugging. Even I tried without any elf file association, still the issue persists
Did anyone face this issue? Please guide me if I'm going wrong somewhere.