The default LLC output frequency in SDP mode is 27 MHz, is there a spec on the accuracy of this signal?
The LLC comes out of a PLL tied to the input signal so it really depends on the input signal. Do you mean if it's free-running? There is no specification for how accurate the free-run 27Mhz is that I've seen.
The free running mode is what I am looking for. I am using this signal to create my 4FSC.
I'm told +/- 5%. There is an app note here: http://www.analog.com/static/imported-files/application_notes/237557357AN_850.pdf that has some relevance to how the clock is generated, FYI.
Thank you Dave. Frank explains it pretty well in the app note.
Have a good day,
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