AnsweredAssumed Answered

Not able to lock ADF4350

Question asked by piyush on May 19, 2011
Latest reply on Apr 30, 2012 by icollins

Hi

For past few days i m working on ADF4350 but not able to achieve lock. I have designed the PCB on FR4 (.8 mm) based on the circuit diagram given in Application Information heading on Pg25 of datasheet. Bottom ground has been provided and since i am using only 1 RF output, the other complimentary output has been terminated with 50 Ohm. Auxilary output is mute. I designed the loop filter values using ADIsim PLL. Required output frequency is 500MHz. I am using Ref Freq=20MHz. Its square wave with 3.3V Amplitude generated by Arbitary function generator with High z output. Loop bandwidth is 100 KHz and PFD freq is 1MHz. Loop filter values comes as: C1 =22.6pF, R1=14.5K,C2=308pF,R2=29.6K,C3=10.3pF. In layout all precautions has been taken like placing decoupling close to supply line etc. I m transfering the control words using serial port of PC. I am using option of Digital Lock Detect, disabled mute till lock detect, prescalar is 8/9 , refrence divider and doubler both have been disabled and since my PFD frequency is 1MHz (>125KHz), i have selected Band Select Clock Divider to 16. I m trying to make ADF4350 work as Integer N PLL, so FRAC is 0. Furthermore Option for Low spur has been enabled.Since my required output should be 500MHz hence output divider is set to 8 and 4GHz of frequency is generated. Loop filter is passive and hence Phase detector polarity is set to 1. Rset is 4.7K and hence Icp is 5 mA. My counter values are as follows:

Output Freq Req: 500MHz    Ref Freq: 20 MHz,     PFD Freq: 1MHz, Output Divider of 8 Modulus selected

R =20 and N=4000

I m sending data and clock thru PC serial port by programing it in C. Programing has been done to take care of Data to CLK setup time Data to Clock hold time CLK to LE setup time, LE pulse width etc. I have verified these waveforms on Oscilloscope and its correct. Initialization sequence is Register 5 -4-3-21-0. Data is transfered as MSB first. Following is my Initialization sequence:

 

                 MSB                                                                                LSB

 

Register5:    0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

 

Register4:    0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 0 0

 

Register3:    0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

 

Register2:    0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 0

 

Register1:    0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

 

Register0:    0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

 

With this control words i m nt getting lock. I m seeing various spurious signals on spectrum analyser and there is a signal of 532 MHz , 0dBm but it doent seems to be phase locked as in low span there is a considerable amount of jitter.

 

Please help me troubleshoot this problem. I have worked on LMX2326 (National Semiconductor) but never faced such kind of problem.  Please help meo out.

 

Regards

Piyush

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