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FPGA evaluation board external FPGA control

Question asked by lds12 on Oct 31, 2015
Latest reply on Nov 2, 2015 by LouijieC


Recently I am trying to control the AD9912 chip in the evaluaion board through the external FPGA.

I have met some problems. I connect the sclk, sdio, and csb  and io_ipdate  four pin ,reset  pin is always o. It seems that the verilog code time sequence is right. I use the external 1Ghz reference as system clock.  still I can not get any output signal except the default one(around 155Mhz). So is that I miss some part of the setting of the evaluation board?

1) Right now the s1 to s4 in the board is high. clock model select is Vdd and I use the writing stream mode(W1-W0)->(1,1,)) to write data to the dds.

So could anyone can give me some suggustions how to control the evaluation board DDS througth the FPGA ?

Thanks sincerely.