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AD9910 OSK-to-output latency and much more

Question asked by Roven on Oct 31, 2015
Latest reply on Nov 4, 2015 by Roven

I have troubles with understanding of this document:

http://www.analog.com/media/en/technical-documentation/data-sheets/AD9910.pdf

 

First, I don't understand, what delay have AD9910 from moment, when I changing signal on OSK pin to moment of applying amplitude changing to output 

(previously I set  bits "OSK enable", "manual OSK external control" in CFR1).

 

Second, when I loading data into CRF1 with changing "clear digital ramp accumulator" bit, what delay have AD9910 in digital ramp modulation mode from

moment, when I set I/O_update pin to logic 1 ("Internal I/O update active" bit = 0 in   CFR2) to moment of applying this change to output?

 

When I loading data into CRF1 with changing "clear phase accumulator" bit, what delay have AD9910 in digital ramp modulation mode from moment, when I set

I/O_update pin to logic 1 ("Internal I/O update active" bit = 0 in   CFR2) to moment of applying this change to output?

 

Third, as I understand from Figure 27 and Figure 38, DDS Block and Digital Ramp Generator have "DDS_CLK" as clock source. In section "DRG Slope Control " 

(page 30) written that F_DDS_CLK = 1/4 * Fsysclk. Thus, I see mistake in formula (1), page 23 and other similar  formulas:
now formula (1) looks like
F_out = ( FTW / (2^32) ) * Fsysclk
and has to be
F_out = ( FTW / (2^32) ) * F_DDS_CLK
or
F_out = ( FTW / (2^32) ) * 1/4 * Fsysclk
Isn't it?

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