I am working on ADSP-BF518 with VDSP++5.0update8.0. I am accessing I2C RTC(DS1338) for my application and configured my SCL as 75MHz.The RTC is having 6 registers for time stamp configuration and i am writing into those registers by configuring BF518 as master. i am writing 8 bytes into RTC from BF518, but what is happening is after writing 7 bytes into slave(RTC) during the ack bit of 7 byte BF518 is stretching the clock and not releasing the bus. In the datasheet it is given that , due to FIFO underflow BF518 will stretch the clock for slave and whenever data is transfered to FIFO the bus will be released. How can we avoid this clock stretching ?
Please suggest me on this issue.