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ADV7612 DDR mode and manual clock selection.

Question asked by tonerm02 on May 11, 2011
Latest reply on May 11, 2011 by tonerm02

 

 

It is my understanding that the ADV7612 8-bit SDR  ITU-R BT.656  output format is limited to SD resolutions. I am attempting to create an 8-bit SDR 4:2:2 stream at 720p using the 8-bit 4:2:2 DDR output format (OP_FORMAT_SEL[7:0]=0x20) and doubling the output pixel clock using the MAN_OP_CLK_SEL_EN and the MAN_OP_CLK_SEL registers. The problem is that setting  MAN_OP_CLK_SEL[2:0] to 001 (2x data clk) has no effect whatsoever on the pixel clock.

 

I am using the EVAL-ADV7612-7511p board.

 

Am I trying to do something impossible? Am I missing something simple in the Hardware user guide / Software manual? Do I have a faulty unit?

 

Interestingly when operating in 2x1 720p decimation mode the pixel clock can be doubled by setting the register MAN_OP_CLK_SEL[2:0] to 111 or 101, both of these values are marked as “Reserved. Do not use”. Using this arraignment I have been able to create an 8-bit SDR 4:2:2 stream at 640x720 (640 pixels wide 720 pixels high). Unfortunately I require a non-decimated 1280x720.

 

-Matt

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