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SYNC_CLK pin  AD9959

Question asked by Georgy on May 10, 2011
Latest reply on May 14, 2011 by Georgy


From datasheet AD9959, AD9958:

  < When FR1<6> = 1and the PWR_DWN_CTL input pin is high, the AD9959 is put into full power-down mode. In this mode, all functions are powered down. This includes the DAC and PLL, which take a significant amount of time to power up ...>

My conditions:

- The REFCLK multiplier bypassed, CLK from external oscillator, 500 MHz.



Are signal (SYSTEM CLK) / 4  at SYNC_CLK pin  In this case?