From datasheet AD9959, AD9958:
< When FR1<6> = 1and the PWR_DWN_CTL input pin is high, the AD9959 is put into full power-down mode. In this mode, all functions are powered down. This includes the DAC and PLL, which take a significant amount of time to power up ...>
- The REFCLK multiplier bypassed, CLK from external oscillator, 500 MHz.
Are signal (SYSTEM CLK) / 4 at SYNC_CLK pin In this case?