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AD7177-2 Sample Clock input - LVPECL levels OK?

Question asked by danstiurcaFCS on Oct 30, 2015
Latest reply on Nov 4, 2015 by JellenieR

Hello,

 

We are working on a 8 ADC system, based on the AD7177-2 ADC.

Can the AD7177-2 sample clock input be driven by LVPECL levels?

 

I would like to use the Hittite HMC987LP5E 1:9 Fanout Buffer as the clock distributor from a 16MHz clock generator.

 

Will this work?

 

Do the SPI clocks need to be synchronized with the sampling clock?

 

Thank you,

Dan

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