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Problem of tx_samp_freq AD9364

Question asked by bhatnagar.vaibhav81 on Oct 30, 2015
Latest reply on Jul 26, 2016 by DragosB

Hello Everybody,

 

I am using ad9364 FMCOMMS4 with KC705. I have HDL ref design for Vivado2014.4.1.

 

In the ref HDL design of AD9364, I use ad9361_clk (single ended version of the differential clock that enters in the FPGA) for my modulator and demodulator that requires a 10MHz clock.

But the clock ad9361 is 20MHz when I generate from the main.c for sampling freq of 10MHz. Why it is not 10MHz, I saw ad9361_clk is been used in your design for wfifo that receives ad_data_i0, q0 at the 10MSPS.

{1280000000,  80000000, 40000000, 20000000,  10000000, 10000000},

{1280000000,  80000000, 40000000, 20000000,  10000000, 10000000},

 

Because, when I used this 20MHz clock in order to generate 10MHz the design does not work.

 

Can somebody please let me know why there is not a 10MHz clock coming out of the ad9361 logic that is synchronized with the adc_data. Please let me know the data has been processed at the dac side with the 20MHz clock in ad9361 HDL logic.

 

Thanks in advance.

 

Best regards,

 

Vaibhav

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