Hello,

1) What is the total SSB phase noise when cascading 3 HMC705LP4E ?

The input is a very clean 3GHz sin wave.

For each chip, the division ratio will be between 1 and 8 (from total bypass to divide by 512).

2) If I understand correctly the "FAQ: HMC Microwave Frequency Dividers by Analog Devices", if the last chip is configured as a divide-by-2, the output's duty cycle will be 50% no matter the division ratio on the other chips ?

Thank you

Hello,

Thank you for your question regarding the cascaded noise of (3) HMC705LP4E's. This is a great question. I think there are a couple of ways to look at this. First, we can derive the expected noise since they add linearly. To do this you'll need to convert the noise from each noise source (3GHz sine wave and each divider) from dBc to mW, add them together and convert back to dBc (1 Hz BW is assumed). I get -148.23dBc /Hz using the nominal -153dBc/Hz (6GHz, N=17) from the datasheet.

You could also measure it. Although each of these dividers will perform similarly with respect to their "residual" or "additive" noise, the instantaneous noise that occurs at any given offset from the carrier will vary for each contributor. This means that depending on the phase, the noise will either add or subtract to some extent at any moment in time. The 'uncertainty' for (3) frequency dividers will be 4.77dB in addition to any other test system uncertainties. Any uncertainties that are both independent of one another and random can be combined using the root-sum of the squares (RSS) to derive a single value for uncertainty.

Hopefully this helps,

Marty