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HMC705LP4E: cascading 3 chips and SSB phase noise

Question asked by jpr on Oct 29, 2015
Latest reply on Oct 30, 2015 by MRichardson



1) What is the total SSB phase noise when cascading 3 HMC705LP4E ?

The input is a very clean 3GHz sin wave.

For each chip, the division ratio will be between 1 and 8 (from total bypass to divide by 512).


2) If I understand correctly the "FAQ: HMC Microwave Frequency Dividers by Analog Devices", if the last chip is configured as a divide-by-2, the output's duty cycle will be 50% no matter the division ratio on the other chips ?


Thank you