we have HSC-ADC-EVALCZ+AD9653, it could sample a sine wave no problem when the sampling clock is below 100 Mhz or so,
above that it shows some spikes on the data. (We use VisualAnalog, the HSC-ADC-EVALCZ is FIFO501B ) ,
It looks like the FPGA firmware has timing issue at higher data rate.
Do you have a fix to this problem?
We would need the ADC work at 125MHz !
Many thanks !