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AD9361 LVDS data clock

Question asked by Z.Y on Oct 28, 2015
Latest reply on Oct 29, 2015 by tlili

Hello everyone,



I am working with the ad9361 chip (ARRADIO daugther card ). The chip is connected to a FPGA in the LVDS mode. After debugging the LVDS interface, I wonder why the data clock have no shift between the P and N clock. I captured the signals on the osciliskop, see attachment.


does someone have an idea why this happens? or get the same problem.


I would welcome your response.