I am working with the ad9361 chip (ARRADIO daugther card http://download.siliconexpert.com/pdfs/2015/6/29/23/49/45/930/tertc_/manual/schematic8.19.14.pdf ). The chip is connected to a FPGA in the LVDS mode. After debugging the LVDS interface, I wonder why the data clock have no shift between the P and N clock. I captured the signals on the osciliskop, see attachment.
does someone have an idea why this happens? or get the same problem.
I would welcome your response.