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Bitstream error trying to evaluate AD9680 on KCU105 board

Question asked by ic70 on Oct 27, 2015
Latest reply on Nov 9, 2015 by ic70
Branched to a new discussion

I have the FMCDAQ2 eval board and the KCU105 fpga board (sold together as a kit by Avnet) that I'm trying to use to eval the adc & dac.

I downloaded the HDL source (hdl_2015_r1) as a zip file.

I also installed Vivado 2014.4.1, as required.

 

I have succeeded in Synthesizing and Implementing the design, but when I generate the bitstream, Vivado says:

ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not supported:

i_system_wrapper/system_i/axi_ad9144_jesd/inst/i_system_axi_ad9144_jesd_0 (jesd204_v6_0_top)

i_system_wrapper/system_i/axi_ad9680_jesd/inst/i_system_axi_ad9680_jesd_0 (jesd204_v6_0_top__parameterized0)

while executing

"write_bitstream -force system_top.bit "

 

I do have a JESD204B IP license (Report IP Status shows it as Purchased), so I don't understand why it isn't generating the bitstream.

Anyone have any ideas?

- Ian

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