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FMCJESDADC1 Vivado reference design question

Question asked by njp on Oct 27, 2015
Latest reply on Oct 27, 2015 by rejeesh



I brought up the FMCJESDADC1 reference design on the 2015_R1 branch in Vivado and have a question. The ADC data for a single channel is 32-bits on the clock "adc_clk" in the design, but this is a 14-bit ADC. Are two samples available each adc_clk? If that is the case, does that make adc_clk's max frequency be 125MHz (since the ADC is max 250MSPS)?